A highly specialized field, commonly referred to as "electronic design automation" (EDA), has evolved to handle the demanding and complicated task of designing semiconductor chips. In EDA, computers are extensively used to automate the design process. Computers are ideally suited to performing tasks associated with the design process because computers can be programmed to reduce or decompose large, complicated circuits into a multitude of much simpler functions. Thereupon, the computers can be programmed to iteratively solve these much simpler functions. Indeed, it has now come to the point where the design process has become so overwhelming that the next generation of integrated circuit (IC) chips cannot be designed without the help of computer-aided design (CAD) systems.
And after the circuit for a new semiconductor chip has been designed and physically laid out, there still remains extensive testing which must be performed to verify that this new design and layout works properly. A multitude of different combinations of test vectors are applied as inputs to the design in order to check that the outputs are correct. In the past, many prior art testing and reliability tools assumed a constant power supply voltage source. This approach was deficient because although the design might be functioning perfectly from a logic standpoint, it might, nevertheless, still not meet specifications due to hidden voltage drop and electromigration problems in interconnect wires. In real life, each of the transistors of a semiconductor circuit consumes a small amount of power (during the logic switching period.). Individually, the voltage drop in the power network attributable to a single transistor is negligible. However, due to rapid advances in semiconductor technology, today's chips can contain upwards of ten million or more transistors. The cumulative effect of all these voltage drops may lead to serious performance degradation or even critical failures. For example, a transistor might be specified to be a logic "0" from 0.0 to 0.7 volts and to be a logic "1" from 3.3 to 2.1 volts. However, due to the voltage drops in the power network, a transistor output might not switch to those specified ranges and thus results in a logic error. And even if a voltage-tolerant CMOS process is used whereby the transistor has more noise margin, its switching speed is detrimentally impacted. Higher power supply voltages makes transistors switch faster, whereas lower voltages makes them switch slower. Consequently, if the voltage in a power network of a circuit drops below a critical level, the speed of that circuit might be reduced to an unacceptable rate.
Another problem which might arise relates to electromigration. It has been established that high current density can cause the metal in the lines distributing the power through the semiconductor chip to migrate along the path of the current flow. Eventually, over a period of time (e.g., several years), this electromigration can result in an open circuit so that power is cut off from parts of the IC, thereby causing the IC to fail. The electromigration may even result in a short circuit which also causes the IC to fail.
Thus, it would be prudent to test for any potential power distribution problems as part of the overall testing and simulation process. However, testing a circuit with millions of transistors is an extremely complex and time-consuming process. It requires expert knowledge and highly skilled EDA specialists. Furthermore, it requires the dedication of a powerful and expensive mainframe computer with gigabytes of memory. Indeed, advances in semiconductor technology has led to submicron designs having even greater numbers of transistors being crammed into ever greater densities at higher levels of complexities which threaten the capability of today's most powerful computers to simulate.
Thus, there exists a need in the prior art for some reliability analysis tool to test and simulate gigantic power network of multi-million transistor submicron IC designs. The present invention provides a unique, efficient solution by implementing a hierarchical scheme. Basically, the present invention extracts an accurate; yet reduced RC model of the power network and current characteristics for each circuit block in the design layout file and then simulates the entire power network of the design with those derived models to determine the current flow and voltage drops in each interconnect wire in the entire circuit at each instance of time, that would otherwise be impossible to simulate due to the prohibitively large memory and CPU time requirement when tried with a conventional flat simulation method. Based on this transistor level simulation, circuit designers can pinpoint where voltage drop and electromigration may pose problems. The designers may then take corrective action before chips are fabricated and sold.